The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor substrate in which a silicon oxide film containing phosphorus and boron is buried in a trench used for isolating elements from each other formed on the same substrate.
In a semiconductor integrated circuit (to be referred to as an LSI hereinafter), a technique for electrically isolating elements from each other formed on the same substrate is necessary. A typical isolation technique is shown in FIGS. 10 and 12.
FIG. 10 shows a p-n isolating method using a p-n junction obtained by forming an n-type semiconductor element region 511a and a p-type semiconductor region 512 on a p-type semiconductor region 516 of a semiconductor substrate 501a.
FIG. 11 shows a LOCOS isolating method for a thick SiO.sub.2 film 513 for isolating an n-type semiconductor region 511b on the p-type semiconductor region 516 of a semiconductor substrate 501b.
FIG. 12 shows a trench isolating method for forming a deep trench 512, reaching the p-type semiconductor region 516, for isolating an n-type semiconductor element region 511c on the p-type semiconductor region 516 of a semiconductor substrate 501c.
In recent years, in order to obtain the high integration density and high-speed operation of an LSI, the trench isolating method having the smallest area for isolation has been popularly used. In the trench isolation method, as shown in FIG. 12, an insulating film 514 is formed on the inner surface of a trench 512, and a polysilicon film 515 having a thermal expansion coefficient close to that of a silicon substrate is generally buried in the trench 512 in which the insulating film 514 is formed.
In reply to a demand of a further high-speed operation of an LSI, a method of decreasing a capacitance between elements by replacing a material buried in the trench 512 with an insulator having a low dielectric constant has been examined.
First, as an insulator to be buried in the trench 512, a silicon dioxide film having a low dielectric constant and good step coverage and formed by low-pressure CVD (Chemical Vapor Deposition) is considered. However, the shape of the film, like an SiO.sub.2 film 8 shown in FIG. 13, is affected by the shape of a trench 2, thereby forming a depression 7 in the SiO.sub.2 film 8 at the upper portion of the trench 2. Therefore, when the SiO.sub.2 film 8 is etched by a depth corresponding to the thickness thereof to remove a part of the SiO.sub.2 film 8 out of the trench 2, the SiO.sub.2 film 8 left in the trench 2 is not suitable for the material to be buried in the trench 2 because the SiO.sub.2 film 8 has a deep depression 7a in the trench 2 like an SiO.sub.2 film 8a shown in FIG. 14.
For this reason, the concept of reflowing (remelting) is used. A silicon oxide film (borophosphosilicate glass; BPSG) is formed in the trench 2 by low-pressure CVD. This silicon oxide film contains boron and phosphorus, has a low dielectric constant, good step coverage, a reflow property better than that of an SiO.sub.2 film doped with no impurity, and a small stress, and does not easily generate stress in the substrate. In this case, as will be described later, as shown in FIG. 16, a BPSG film 5 has a depression 7 at the upper portion of the trench 2 immediately after the BPSG film 5 is formed. However, when the BPSG film 5 is reflowed at a temperature of 900.degree. C. to 1,000.degree. C., the surface of the BPSG film 5 is smoothed as shown in FIG. 17. Therefore, when the BPSG film 5 is etched by a depth corresponding to the thickness thereof at the flat portion, a BPSG film 5b having a flat upper portion which is suitable for the material to be buried in the trench 2 is formed in the trench 2.
A conventional method of manufacturing a semiconductor device using a BPSG-buried trench will be described below with reference to the accompanying drawings.
FIGS. 15 to 21 are sectional views showing the main steps in manufacturing a semiconductor device by a conventional manufacturing method. As shown in FIG. 15, a trench 2 having a width of about 0.6 to 1.0 .mu.m and a depth of 4 to 6 .mu.m is formed in a semiconductor device 1, and an SiO.sub.2 film 3 and an Si.sub.3 N.sub.4 film 4 are sequentially formed on the surface of the semiconductor substrate 1 and the inner surface of the trench 2. The Si.sub.3 N.sub.4 film 4 serves as a stopper for preventing phosphorus and boron in a BPSG film buried in the trench 2 (to be described later) from being diffused in the semiconductor substrate 1 when a barrier film and the BPSG film are etched. The thickness of the Si.sub.3 N.sub.4 film 4 is about 50 to 150 nm (nanometer). Furthermore, the SiO.sub.2 film 3 is used for preventing a stress generated when the Si.sub.3 N.sub.4 film 4 is brought into direct contact with the semiconductor substrate 1 and has a thickness of about 30 to 200 nm. As shown in FIG. 16, a BPSG film 5 having a phosphorus concentration of 2 to 6 mol % and a boron concentration of 8 to 12 mol % is formed on the Si.sub.3 N.sub.4 film 4 by low-pressure CVD to sufficiently bury the trench 2 and to have a thickness t1 which is 1/2 or more a width t2 of the trench 2 (t1.gtoreq.t2/2). At this time, the BPSG film 5 has a depression 7 at the upper portion of the trench 2. The BPSG film 5 is reflowed by annealing at a temperature of 900.degree. C. to 1,000.degree. C. to smooth the surface of the BPSG film 5, thereby obtaining a BPSG film 5a shown in FIG. 17. The BPSG film 5a is etched using an etching liquid containing hydrofluoric acid by a depth corresponding to the thickness of the BPSG film 5a at a flat portion thereof to leave a BPSG film 5b in the trench 2 as shown in FIG. 18, so that the upper end of the BPSG film 5b has the same level as that of the surface of the semiconductor substrate 1. An unnecessary part of the Si.sub.3 N.sub.4 film 4 on the surface of the semiconductor substrate 1 is etched using phosphoric acid heated at a temperature of 140.degree. to 160.degree. C. to expose the SiO.sub.2 film on the surface of the semiconductor substrate 1, and an Si.sub.3 N.sub.4 film 4 a is left in the trench 2 as shown in FIG. 19. At this time, since the SiO.sub.2 film 3 exposed on the semiconductor substrate 1 is exposed to the phosphoric acid used for etching the Si.sub.3 N.sub.4 film 4, the SiO.sub.2 film 3 has poor thickness controllability and poor film quality, and the SiO.sub.2 film 3 cannot be used as a substrate protecting film for ion implantation or a gate oxide film of a MOS transistor. Therefore, the SiO.sub.2 film 3 must be reformed. As shown in FIG. 20, the SiO.sub.2 film 3a is left in the trench 2 and the SiO.sub.2 film 3 on the surface of the semiconductor substrate 1 is partially etched by an etching liquid containing hydrofluoric acid. As shown in FIG. 21, the exposed surface of the semiconductor substrate 1 is thermally oxidized to form an SiO.sub.2 film 30. The SiO.sub.2 film 30 has a thickness required in the next step.
Subsequently, elements are formed on the semiconductor substrate 1 by a normal process. As described above, the BPSG film 5b having a dielectric constant lower than that of polysilicon is buried in the trench 2 for isolation, thereby manufacturing an LSI having a decreased capacitance between the elements.
In the conventional manufacturing method, since annealing at a temperature of 850.degree. C. to 1,100.degree. C. is performed while the surface of the semiconductor substrate and the BPSG film in the trench are exposed as shown in FIG. 14, phosphorus and boron in the BPSG film are diffused out as indicated by arrows in FIGS. 22 and 23, thereby forming an impurity diffusion region 9 in the semiconductor substrate 1 around the trench. Even when annealing (thermal oxidation) is performed at a temperature of 1,000.degree. C. for 30 minutes, the impurity diffusion region 9 has a width of 0.5 .mu.m or more on each side of the trench. Even when micropatterning is performed to obtain a trench having a width of 0.8 .mu.m, when the SiO.sub.2 film formed on the inner wall of the trench extends to the semiconductor substrate 1 to have a width of 0.1 .mu.m, and an impurity diffusion region formed by diffusion from the BPSG 5b has a width of 0.5 .mu.m on each side of the trench. In this case, an isolation region has the width of 2.0 .mu.m as shown in FIG. 9A, and the high integration density of an LSI cannot be easily obtained.